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02/12/09 www.irf.com 1 hexfet power mosfet benefits optimized for logic level drive very low r ds(on) at 4.5v v gs superior r*q at 4.5v v gs improved gate, avalanche and dynamic dv/dt ruggedness fully characterized capacitance and avalanche soa enhanced body diode dv/dt and di/dt capability lead-free applications dc motor drive high efficiency synchronous rectification in smps uninterruptible power supply high speed power switching hard switched and high frequency circuits s d g 97369 IRLB4030PBF gds gate drain source to-220ab v dss 100v r ds ( on ) typ. 3.4m ? max. 4.3m ? i d 180a absolute maximum ratings symbol parameter units i d @ t c = 25c continuous drain current, v gs @ 10v i d @ t c = 100c continuous drain current, v gs @ 10v a i dm pulsed drain current p d @t c = 25c maximum power dissipation w linear derating factor w/c v gs gate-to-source voltage v dv/dt peak diode recovery v/ns t j operating junction and c t stg storage temperature range soldering temperature, for 10 seconds (1.6mm from case) mounting torque, 6-32 or m3 screw avalanche characteristics e as (thermally limited) sin g le pulse avalanche ener g y mj i ar avalanche current a e ar repetitive avalanche ener g y mj thermal resistance symbol parameter typ. max. units r jc junction-to-case ??? 0.40 c/w r cs case-to-sink, flat, greased surface 0.50 ??? r ja junction-to-ambient ??? 62 305 see fig. 14, 15, 22a, 22b, 370 21 -55 to + 175 16 2.5 10lb in (1.1n m) 300 max. 180 130 730

2 www.irf.com repetitive rating; pulse width limited by max. junction temperature. limited by t jmax , starting t j = 25c, l = 0.05mh r g = 25 ? , i as = 110a, v gs =10v. part not recommended for use above this value . i sd 110a, di/dt 1330a/s, v dd v (br)dss , t j 175c. pulse width 400s; duty cycle 2%. s d g c oss eff. (tr) is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 to 80% v dss . c oss eff. (er) is a fixed capacitance that gives the same energy as c oss while v ds is rising from 0 to 80% v dss . when mounted on 1" square pcb (fr-4 or g-10 material). for recommended footprint and soldering techniquea refer to applocation note # an- 994 echniques refer to application note #an-994.
static @ t j = 25c (unless otherwise specified) symbol parameter min. typ. max. units v (br)dss drain-to-source breakdown volta g e 100 ??? ??? v ? v (br)dss / ? t j breakdown volta g e temp. coefficient ??? 0.10 ??? v/c r ds(on) static drain-to-source on-resistance ??? 3.4 4.3 m ? ??? 3.6 4.5 v gs(th) gate threshold volta g e 1.0 ??? 2.5 v i dss drain-to-source leaka g e current ??? ??? 20 ??? ??? 250 i gss gate-to-source forward leaka g e ??? ??? 100 gate-to-source reverse leaka g e ??? ??? -100 r g(int) internal gate resistance ??? 2.1 ??? ? dynamic @ t j = 25c (unless otherwise specified) symbol parameter min. typ. max. units g fs forward transconductance 320 ??? ??? s q g total gate char g e ??? 87 130 q gs gate-to-source char g e ??? 27 ??? q gd gate-to-drain ("miller") char g e ??? 45 ??? q sync total gate char g e sync. (q g - q gd ) ??? 42 ??? t d(on) turn-on delay time ??? 74 ??? t r rise time ??? 330 ??? t d(off) turn-off delay time ??? 110 ??? t f fall time ??? 170 ??? c iss input capacitance ??? 11360 ??? c oss output capacitance ??? 670 ??? c rss reverse transfer capacitance ??? 290 ??? c oss eff. (er) effective output capacitance (energy related) ??? 760 ??? c oss eff. (tr) effective output capacitance (time related) ??? 1140 ??? diode characteristics symbol parameter min. typ. max. units i s continuous source current (body diode) i sm pulsed source current (body diode) v sd diode forward volta g e ??? ??? 1.3 v t rr reverse recovery time ??? 50 ??? t j = 25c v r = 85v, ??? 60 ??? t j = 125c i f = 110a q rr reverse recovery char g e ??? 88 ??? t j = 25c di/d t = 100a/ s ??? 130 ??? t j = 125c i rrm reverse recovery current ??? 3.3 ??? a t j = 25c t on forward turn-on time intrinsic turn-on time is ne g li g ible (turn-on is dominated by ls+ld) conditions v ds = 25v, i d = 110a i d = 110a v gs = 16v v gs = -16v mosfet symbol showing the v ds = 50v conditions v gs = 4.5v v gs = 0v v ds = 50v ? = 1.0mhz v gs = 0v, v ds = 0v to 80v v gs = 0v, v ds = 0v to 80v t j = 25c, i s = 110a, v gs = 0v integral reverse p-n junction diode. conditions v gs = 0v, i d = 250a reference to 25c, i d = 5ma v gs = 10v, i d = 110a v ds = v gs , i d = 250a v ds = 100v, v gs = 0v v ds = 100v, v gs = 0v, t j = 125c i d = 110a r g = 2.7 ? v gs = 4.5v v dd = 65v i d = 110a, v ds =0v, v gs = 4.5v a ??? ??? ??? ??? v gs = 4.5v, i d = 92a ns nc 180 730 a na nc ns pf

www.irf.com 3 fig 1. typical output characteristics fig 3. typical transfer characteristics fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage 1 2 3 4 5 v gs , gate-to-source voltage (v) 1.0 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) t j = 25c t j = 175c v ds = 50v 60s pulse width -60 -40 -20 0 20 40 60 80 100 120 140 160 180 t j , junction temperature (c) 0.0 0.5 1.0 1.5 2.0 2.5 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( n o r m a l i z e d ) i d = 110a v gs = 10v 1 10 100 v ds , drain-to-source voltage (v) 100 1000 10000 100000 c , c a p a c i t a n c e ( p f ) v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd c oss c rss c iss 0 20406080100 q g , total gate charge (nc) 0.0 1.0 2.0 3.0 4.0 5.0 v g s , g a t e - t o - s o u r c e v o l t a g e ( v ) v ds = 80v v ds = 50v i d = 110a 0.1 1 10 100 1000 v ds , drain-to-source voltage (v) 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) vgs top 15v 10v 8.0v 4.5v 3.5v 3.0v 2.7v bottom 2.5v 60s pulse width tj = 25c 2.5v 0.1 1 10 100 1000 v ds , drain-to-source voltage (v) 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 2.5v 60s pulse width tj = 175c vgs top 15v 10v 8.0v 4.5v 3.5v 3.0v 2.7v bottom 2.5v

4 www.irf.com fig 8. maximum safe operating area fig 10. drain-to-source breakdown voltage fig 7. typical source-drain diode forward voltage fig 11. typical c oss stored energy fig 9. maximum drain current vs. case temperature fig 12. maximum avalanche energy vs. draincurrent 0.0 0.5 1.0 1.5 2.0 2.5 v sd , source-to-drain voltage (v) 0.1 1 10 100 1000 i s d , r e v e r s e d r a i n c u r r e n t ( a ) t j = 25c t j = 175c v gs = 0v 25 50 75 100 125 150 175 t c , case temperature (c) 0 20 40 60 80 100 120 140 160 180 200 i d , d r a i n c u r r e n t ( a ) -60 -40 -20 0 20 40 60 80 100 120 140 160 180 t j , temperature ( c ) 90 95 100 105 110 115 120 125 v ( b r ) d s s , d r a i n - t o - s o u r c e b r e a k d o w n v o l t a g e ( v ) id = 5ma -20 0 20 40 60 80 100 120 v ds, drain-to-source voltage (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 e n e r g y ( j ) 0 1 10 100 1000 v ds , drain-to-source voltage (v) 1 10 100 1000 10000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) operation in this area limited by r ds (on) tc = 25c tj = 175c single pulse 100sec 1msec 10msec dc 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 200 400 600 800 1000 1200 1400 e a s , s i n g l e p u l s e a v a l a n c h e e n e r g y ( m j ) i d top 17a 40a bottom 110a

www.irf.com 5 fig 13. maximum effective transient thermal impedance, junction-to-case fig 14. typical avalanche current vs.pulsewidth fig 15. maximum avalanche energy vs. temperature notes on repetitive avalanche curves , figures 14, 15: (for further info, see an-1005 at www.irf.com) 1. avalanche failures assumption: purely a thermal phenomenon and failure occurs at a temperature far in excess of t jmax . this is validated for every part type. 2. safe operation in avalanche is allowed as long ast jmax is not exceeded. 3. equation below based on circuit and waveforms shown in figures 16a, 16b. 4. p d (ave) = average power dissipation per single avalanche pulse. 5. bv = rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. i av = allowable avalanche current. 7. ? t = allowable rise in junction temperature, not to exceed t jmax (assumed as 25c in figure 14, 15). t av = average time in avalanche. d = duty cycle in avalanche = t av f z thjc (d, t av ) = transient thermal resistance, see figures 13) p d (ave) = 1/2 ( 1.3bvi av ) = t/ z thjc i av = 2 t/ [1.3bvz th ] e as (ar) = p d (ave) t av 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 50 100 150 200 250 300 350 e a r , a v a l a n c h e e n e r g y ( m j ) top single pulse bottom 1.0% duty cycle i d = 110a 1.0e-06 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 tav (sec) 0.1 1 10 100 1000 a v a l a n c h e c u r r e n t ( a ) 0.05 duty cycle = single pulse 0.10 allowed avalanche current vs avalanche pulsewidth, tav, assuming ? j = 25c and tstart = 150c. 0.01 allowed avalanche current vs avalanche pulsewidth, tav, assuming ? tj = 150c and tstart =25c (single pulse) 1e-006 1e-005 0.0001 0.001 0.01 0.1 t 1 , rectangular pulse duration (sec) 0.0001 0.001 0.01 0.1 1 t h e r m a l r e s p o n s e ( z t h j c ) c / w 0.20 0.10 d = 0.50 0.02 0.01 0.05 single pulse ( thermal response ) notes: 1. duty factor d = t1/t2 2. peak tj = p dm x zthjc + tc ri (c/w) i (sec) 0.0477 0.000071 0.1631 0.000881 0.1893 0.007457 j j 1 1 2 2 3 3 r 1 r 1 r 2 r 2 r 3 r 3 c ci i / ri ci= i / ri

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fig 16. threshold voltage vs. temperature

-75 -50 -25 0 25 50 75 100 125 150 175 t j , temperature ( c ) 0.0 0.5 1.0 1.5 2.0 2.5 v g s ( t h ) , g a t e t h r e s h o l d v o l t a g e ( v ) i d = 250a i d = 1.0ma i d = 1.0a 0 200 400 600 800 1000 di f /dt (a/s) 80 160 240 320 400 480 560 640 720 800 q r r ( a ) i f = 73a v r = 85v t j = 25c t j = 125c 0 200 400 600 800 1000 di f /dt (a/s) 80 160 240 320 400 480 560 640 720 800 880 q r r ( a ) i f = 110a v r = 85v t j = 25c t j = 125c 0 200 400 600 800 1000 di f /dt (a/s) 0 5 10 15 20 25 30 35 i r r m ( a ) i f = 110a v r = 85v t j = 25c t j = 125c 0 200 400 600 800 1000 di f /dt (a/s) 0 5 10 15 20 25 30 35 40 i r r m ( a ) i f = 73a v r = 85v t j = 25c t j = 125c

www.irf.com 7 fig 23a. switching time test circuit fig 23b. switching time waveforms fig 22b. unclamped inductive waveforms fig 22a. unclamped inductive test circuit t p v (br)dss i as r g i as 0.01 ? t p d.u.t l v ds + - v dd driver a 15v 20v v gs fig 24a. gate charge test circuit fig 24b. gate charge waveform vds vgs id vgs(th) qgs1 qgs2 qgd qgodr fig 21.
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p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-applied voltage reverse recovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period + - + + + - - - ? ? ! "#"" ?
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d.u.t. v ds i d i g 3ma v gs .3 f 50k ? .2 f 12v current regulator same type as d.u.t. current sampling resistors + - v ds 90% 10% v gs t d(on) t r t d(off) t f
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to-220ab packages are not recommended for surface mount application. data and specifications subject to change without notice. this product has been designed and qualified for the industrial market. qualification standards can be found on ir?s web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 02/09

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